Xcell Magazine Article Warren Miller 06/19/01 Rev 1.2

A Hardware Reference Design for Xilinx Reed-Solomon LogiCore-

Uses New IP Development Environment to Accelerate Simulation and Development Time

Introduction

Reed-Solomon codes provide the foundation for successful communications in noisy environments. Because these codes allow several errors to be detected and corrected without the need to retransmit the data they provide increased bandwidth as well as improved data integrity in error inducing communications channels. A hardware reference design has been created using standard Avnet developed evaluation kits to demonstrate the functionality of two Xilinx LogiCore Reed-Solomon IP cores in an error prone system.

Short Description of Core

Reed-Solomon codes are one of the most efficient and common error correction codes used in communications applications. Common items like CD and DVD players use Reed-Solomon codes as well as wireless and wired communications systems. Because this type of code is very good at correcting burst errors, it is used in applications where noise or defects can take out a series of information bits. Other codes (like Hamming codes) are better suited for more random error patterns (like in memory systems) where only a bit at a time is affected.

Reed-Solomon codes append a series of symbols (check words) to a series of information symbols (data words). The check words are constructed (similar to the familiar parity check) such that if errors are introduced anywhere in the data, the correct data can be reconstructed. The number of errors that can be corrected is one half the number of check symbols (rounded down). For 8 bit wide data words, a common code has a block size of 207 words with 20 check symbols and 187 data symbols. This is the example code we will use in the reference design.

Description of Hardware Implementation

The reference design includes a Data Generator (which creates an input data stream), a Reed-Solomon Encoder (which takes blocks of input data and creates the check symbols), an Error Generator (which injects controlled pseudo-random error patterns into the communications channel) and the Reed-Solomon Decoder (which detects and corrects errors in the transmitted data). As shown in Figure 1, the Data Generator and Encoder reside on an Avnet designed Spartan2 evaluation board. The data block with appended check words is transferred to the Virtex evaluation board where the data is received and corrected by the Decoder.

The Error Generator uses a pseudo-random number generator to select errors to inject into the information block. Up to 10 errors are injected at random locations in the information stream to simulate a noisy channel. This verifies the functionality of both the Encoder and the Decoder since when there are no errors, it is not clear that anything is actually being done by the reference design. To easily see the results of the processing of the decoder in the Reference Design, an IP Development Tool that works with the Avnet Virtex Development Board is used.

Description of Raptor Development Environment

The Raptor IP Development Environment is an integrated software and firmware tool, which works in conjunction with the Avnet Virtex Development Kit, to accelerate the development, integration and test of IP or IP based Xilinx FPGA designs. Raptor automatically inserts logic around any IP Core to route inputs and outputs to real-time input signals, output signals, and buffer memory available on the development board. This allows the Core to be exercised at ‘hardware speeds’. Core output signals that are stored in the buffer memory can be read out over the USB port to a host computer and displayed on the waveform viewer, just like they were software simulation results. This ‘hardware speed’ approach to verification reduces the design/debug cycle time dramatically, making it easy to make design or test set-up changes and see the results immediately. Used in conjunction with hardware based input stimulus, verification of very complex and robust test suites are orders of magnitude faster than pure software simulation based approaches.

The Raptor User Interface, shown in figure 2, allows the user to specify the inputs and outputs to their IP. The necessary logic is automatically added around the users IP and then compiled using the Xilinx development tools, Foundation in this example. The user core is then exercised by the hardware and the results are read out of memory and transferred to the PC over the USB port. The signals can be displayed on a waveform display- a sample output is shown in figure 3. Because the signals are run at hardware speeds hundreds of thousands of cycles can be run, orders of magnitude faster than software only simulations.

Conclusion

Reed-Solomon Codes are a basic building block of many digital communications systems. The Xilinx LogiCore Encoder and Decoder were easily ported to the Avnet Development boards, using the Raptor IP Development system from Experience First. For more information on Avnet Development Boards or the Raptor IP Development Environment contact Warren Miller at Avnet Design Services (warren.miller@avnet.com).