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The Path to Successful ASIC Design

TESTBENCH
A testbench is written based on the customer specifications for the design
           FINAL VERIFICATION
Varification of front and back end database
             
  FUNCTIONAL SIMULATION
Validation of the database occurs at this point
 SYNTHESIS & TEST SIMULATIONS
JTAG is supported
 STATIC TIMING GATE LEVEL SIMULATIONS
Validation of timing
 FLOORPLAN
Preliminary strategy planning for design layout
 PLACE & ROUTE
Final transition to back and design
 TIMING VERIFICATION
Validation of timing using back annotated parasitics
             
RTL
Register Transfer Logic
         IN PLACE OPTIMIZATION
Re-arrangment of cells to archive timing
  
             
      CUSTOM WIRE LOAD SYSTHESIS
Back annotation of parasitics